The present invention relates to semiconductor memory devices, and more particularly, to electrode contact structures in semiconductor memory devices and methods of fabricating the same.
Many efforts have been made to improve the performance of semiconductor memory devices. In particular, various techniques have been introduced to improve conventional equal-interval matrix type memory cells, such as folded bitline structure memory cells. For example, diagonal memory cells have been developed. In a diagonal memory cell, the bitlines extend in an oblique direction relative to an active region, forming an oblique angle therebetween.
However, in a cell structure where the bitlines are oblique relative to the active region, the distance between lower electrode contact structures for capacitors may be decreased. This decreased distance between the lower electrode contacts may cause problems. In particular, due to the decreased distance between contacts, the lower electrode contacts may electrically contact the bitlines, which may cause a short circuit. U.S. Pat. No. 6,621,110 to Matsuoka et al. discloses a semiconductor integrated circuit device and a method of manufacturing the same that may address some of these problems.
FIG. 1 is a plan view of a conventional semiconductor memory device having lower electrode contact structures as shown in U.S. Pat. No. 6,621,110. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.
Referring now to FIGS. 1 and 2, a first interlayer insulating layer 30, a second interlayer insulating layer 32, and a third interlayer insulating layer 34 are sequentially deposited on a semiconductor substrate 10 having an active region 14 therein. The active region 14 is defined by a device isolation region 12. The first interlayer insulating layer 30 includes a lower electrode contact pad 16. The second interlayer insulating layer 32 includes a TiN layer 18. The TiN layer 18 may function as an adhesive layer, connecting the lower electrode contact pad 16 to a bitline 20 formed on an upper surface of the second interlayer insulating layer 32. The second interlayer insulating layer 32 and the third interlayer insulating layer 34 include a lower electrode contact plug 22 electrically connecting the lower electrode contact pad 16 to a capacitor lower electrode (not shown). The bitline 20 extends in an oblique direction relative to a word line 2 that is perpendicular to the active region 14.
The distance between centers of adjacent contact plugs 22 on opposite sides of the bitline 20 is greater than 2 F, where F is the width of the word line 2 and/or the bitline 20. The diameter of the lower electrode contact plug 22 is less than that of the lower electrode contact pad 16. As such, the lower electrode contact plug 22 may be formed off-center on the lower electrode contact pad 16 in order to increase the distance between the lower electrode contact plug 22 and the bitline 20. Thus, electrical contact (i.e., a short circuit) between the bitline 20 and the lower electrode contact plug 22 may be prevented. Since the diameter of the lower electrode contact plug 22 is less than that of the lower electrode contact pad 16, sufficient contact between the plug 22 and the pad 16 can be maintained without an increase in contact resistance.
However, where the distance between centers of the lower electrode contact plugs 22 is less than 2 F, it may be difficult to maintain a distance between the lower electrode contact plugs 22 and the bitlines 20 sufficient to prevent electrical contact therebetween. In addition, it may be difficult to maintain sufficient contact area between the lower electrode contact pad 16 and the lower electrode contact plug 22, even if the lower electrode contact plug 22 is formed using self-alignment techniques. More particularly, sufficient contact may not be maintained when a misalignment between the lower electrode contact pad 16 and the lower electrode contact plug 22 is greater than about 15 nm. In other words, when the lower electrode contact plug 22 extends beyond (i.e., overhangs) an edge of the lower electrode contact pad 16 by more than about 15 nm, contact resistance may be increased due to the reduction in contact area.